1. Field of the Invention
This invention relates in general to the field of instruction execution in computers, and more particularly to an apparatus and method for executing a compare-and-jump operation.
2. Description of the Related Art
Conditional jump instructions are common to all present day microprocessor instruction sets. The conditional jump instruction allows a programmer to direct a microprocessor to evaluate the status of the microprocessor due to execution of previous instructions and to redirect program control flow based upon the findings of the evaluation. Most often, a conditional jump instruction specifies that the contents of a result status register, or flags register, are to be evaluated against a prescribed condition. The flags register contains bits, or flags, that are set when a result is generated by an arithmetic logic unit (ALU) in the microprocessor. The flags are set to indicate the condition of the result. For example, an ALU instruction directing the microprocessor to add two operands would be executed by the ALU and following generation of the sum, the flags register would be updated. If the sum is zero, then a zero flag in the flags register is set. If the sum is a negative number, then a sign flag is set. Use of the conditional jump instruction allows a programmer to make program control decisions about certain attributes, or conditions, of the generated result without having to specifically examine the result itself. The programmer may desire to direct program control to another location if the result is zero, in which case he/she would program a conditional jump instruction following an ALU instruction that prescribes a jump to a target address if the zero flag in the flags register is set.
ALU instructions most often perform operations using operands that are provided to the ALU. These operands can be provided directly by an ALU instruction, they can be provided from a register file within a microprocessor, or they must be first fetched from memory that is external to the microprocessor. In addition, the result of an ALU instruction is either written directly to a register in the microprocessor or it must be stored in a memory location. When an ALU instruction must first be loaded from memory, it is referred to as a load-ALU instruction. If the result is to be stored in memory, the ALU instruction is referred to as an ALU-store instruction. If the operand is to be fetched from memory and the result is to be stored in memory, the ALU instruction is referred to as a load-ALU-store instruction. Instructions such as these are commonly employed by stand alone in application programs and they are also employed in conjunction with conditional jump instructions as described above.
A present day microprocessor is divided into stages, with each stage dedicated to performing a specific function. A programmed instruction is first decoded into an associated sequence of micro instructions, with each micro instruction in the sequence directing the microprocessor to perform a specific task related to an overall operation that is prescribed by the programmed instruction. These micro instructions are placed in a queue and are then synchronously executed in sequential stages of the microprocessor through completion. Micro instructions are specifically designed to operate in accordance with both the capabilities and limitations of a particular microprocessor architecture. A micro instruction cannot prescribe a task that logic within a given stage of the microprocessor cannot perform. Stated differently, translation of an ALU instruction into a corresponding sequence of micro instructions involves decomposition of the operation prescribed by the ALU instruction into discrete tasks, each of which can be executed by a single micro instruction.
One of the limitations of present day microprocessors is that logic to access memory is typically contained within the same stage as the ALU. Hence, a micro instruction can specify a read from memory, a write to memory, or an ALU operation. With rare exception, it cannot specify a combined memory access and ALU operation. This is a problem. Because of this, a load-ALU-store instruction requires translation into three micro instructions: a first micro instruction to load an operand from memory, a second micro instruction to perform the ALU operation, and a third micro instruction to store the result of the operation to memory.
A compare-and-jump operation is specified by immediately following an ALU instruction with a conditional jump instruction. And although the two instructions are related, present day microprocessors treat them independently. The ALU instruction is translated into a sequence of micro instructions directing the ALU operation and the conditional jump instruction is translated into a conditional jump micro instruction directing the microprocessor to evaluate the flags register following generation of the result of the ALU operation. Hence, to perform a compare-and-jump operation involving a load-ALU-store instruction would require four micro instructions: the three micro instructions noted above plus a following conditional jump micro instruction.
The time required to execute any operation on a microprocessor is directly related to the number of micro instructions that are required to implement the operation within the stage design of the microprocessor. In the examples cited above, execution of load-ALU-store operations take three micro instructions; execution of a load-ALU-store-jump operation requires four micro instructions. One skilled in the art will appreciate that an application program that exhibits a significant number of these types of operations will incur notable execution delays, simply because a micro instruction cannot prescribe a combined memory access and ALU task.
Therefore, what is needed is a microprocessor that allows a micro instruction to specify a combined memory access and ALU task.
In addition, what is needed is a microprocessor that can execute a load-ALU-store instruction and a compare-and-jump operation much faster than has heretofore been provided.
Furthermore, what is needed is an apparatus in a microprocessor that allows a single micro instruction to prescribe a load-ALU-store-jump operation.
Moreover, what is needed is a method for combining a conditional jump instruction and an ALU instruction into a single compare-and-jump micro instruction.
To address the above-detailed deficiencies, it is an object of the present invention to provide a microprocessor that can load an operand from memory, perform an ALU operation, and store a result in memory, where all three of these tasks are prescribed by a single micro instruction.
Accordingly, in the attainment of the aforementioned object, it is a feature of the present invention to provide a microprocessor for performing a load-ALU-store operation. The microprocessor includes translation logic, load logic, execution logic, and store logic. The translation logic receives a load-ALU-store macro instruction and decodes the load-ALU-store macro instruction into a load-ALU-store micro instruction. The load-ALU-store micro instruction directs the microprocessor to retrieve an operand from a location in memory, to perform an ALU operation using the operand, and to store a result to the location in the memory. The load logic is coupled to the translation logic and retrieves the operand from the location. The execution logic is coupled to the load logic. The execution logic performs the ALU operation and provides the result. The store logic is coupled to the execution logic. The store logic receives the result and stores the result in the location. The translation logic employs a control ROM to decode the load-ALU-store macro instruction.
An advantage of the present invention is that only one micro instruction is required to implement a load-ALU-store operation.
Another object of the present invention is to provide a microprocessor that can execute a compare-and-jump operation much faster than has heretofore been provided.
In another aspect, it is a feature of the present invention to provide an apparatus in a microprocessor for executing a compare-and-jump operation. The apparatus has a jump combiner, execution logic, and store logic. The jump combiner detects an ALU micro instruction and a conditional jump micro instruction, indicates a condition test prescribed by the conditional jump micro instruction in a field of said ALU micro instruction, and deletes the conditional jump micro instruction. The execution logic is coupled to the jump combiner. The execution logic receives the ALU micro instruction and performs an ALU operation prescribed by the ALU micro instruction. The execution logic also generates a result of the ALU operation and updates a flags register to indicate a condition of the result. The store logic is coupled to the execution logic. The store logic receives the result and performs the condition test on the flags register as prescribed by the field. The compare-and-jump operation is prescribed by the ALU micro instruction and the conditional jump micro instruction. The ALU operation is a binary arithmetic operation, a decimal arithmetic operation, or a logic operation.
Another advantage of the present invention is that application programs having a significant number of compare-and-jump operations execute without undue program delays.
A further object of the invention is to provide an apparatus in a microprocessor that allows a single micro instruction that accomplishes all three tasks related to a load-ALU-store instruction: loading an operand from memory, performing an ALU operation using the operand, and storing a result of the operation.
In a further aspect, it is a feature of the present invention to provide an apparatus for executing a compare-and-jump macro instruction sequence directing a microprocessor to perform a compare function, to update a flags register with a status corresponding to a result, and to evaluate the flags register to determine if the status satisfies a prescribed condition. The apparatus includes an instruction decoder and a jump combiner. The instruction decoder receives the compare-and-jump macro instruction sequence and translates the macro instruction sequence into an ALU micro instruction and a conditional jump micro instruction. The jump combiner is coupled to the instruction decoder. The jump combiner combines the ALU micro instruction and the conditional jump micro instruction into a compare-and-jump micro instruction. The compare-and-jump micro instruction has an ALU micro operation field and a conditional jump field. The ALU micro operation field directs the microprocessor to perform the compare function and to update the flags register with the status. The conditional jump field directs the microprocessor to evaluate the flags register.
A further advantage of the present invention is that the number of instructions to implement a compare-and-jump operation actually decreases as they are processed by the microprocessor.
Yet another object of the present invention is to provide a method for combining a conditional jump instruction and an ALU instruction into a single compare-and-jump micro instruction.
In yet another aspect, it is a feature of the present invention to provide a method for performing a compare-and-branch operation in a pipeline microprocessor. The method includes detecting an ALU micro instruction and a conditional branch micro instruction prior to their execution, combining the ALU instruction and the conditional jump instruction into a compare-and-branch micro instruction, performing a compare operation prescribed by the compare-and-branch micro instruction to produce a result and a result status, and evaluating the result status in accordance with a condition prescribed by the compare-and-branch micro instruction. The detecting includes monitoring a micro instruction queue to identify the conditional branch micro instruction, and confirming that the conditional branch micro instruction immediately follows the ALU micro instruction in the micro instruction queue.
Yet another advantage of the present invention is that execution of a conditional branch operation can be combined with execution of a related ALU operation.